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NCP1603 PFC/PWM Combo Controller with Integrated High Voltage Startup and Standby Capability
The NCP1603 is a Power Factor Correction (PFC) and Pulse Width Modulation (PWM) combo controller. It offers extremely low no-load standby power consumption that is suitable for the low-power consumer markets. The key features of the device are listed below.
Features
1
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MARKING DIAGRAM
16 SO-16 D SUFFIX CASE 751B 1 1603D100G AWLYWW
* Pb-Free Package is Available*
PFC Features
* Near-Unity Power Factor in Discontinuous and Critical Mode * * * * * * * * *
(DCM and CRM) Voltage-Mode Operation Low Startup and Shutdown Current Consumption Programmable Switching Frequency for DCM Synchronization Capability Overvoltage Protection (107% of Nominal Output Level) Undervoltage Protection or Shutdown (8% of Nominal Output Level) Programmable Overcurrent Protection Thermal Shutdown with Hysteresis (95/140C) Undervoltage Lockout with Hysteresis (9.0/10.5 V)
A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PIN CONNECTIONS
Vaux 1 FB2 2 CS2 3 GND2 4 Osc 5 GND1 6 Out1 7 VCC1 8 (Top View) 16 HV 15 NC 14 VCC2 13 Out2 12 Ramp 11 CS1 10 Vcontrol 9 FB1
PWM Features
* Integrated Lossless High Voltage Startup Current Source * 100 kHz PWM Current-Mode Operation with Skipping Cycle * * * * * * *
Capability During Standby Condition PFC Bias Voltage is Disabled in Standby Condition to Achieve Extremely Low No-Load Standby Power Consumption Fault Protection Implemented by a Timer and Independent of Badly Coupled Auxiliary Transformer Winding Primary Overcurrent Protection and Latched Overvoltage Protection Internal 2.5 ms Soft-Start "6.4% Frequency Jittering for Improved EMI Performance Latched Thermal Shutdown with Hysteresis (140/165C) Undervoltage Lockout with Hysteresis (5.6/7.7/12.6 V)
ORDERING INFORMATION
Device NCP1603D100R2 NCP1603D100R2G Package SO-16 Shipping 2500 Tape & Reel
SO-16 2500 Tape & Reel (Pb-Free)
Applications
* Notebook Adapters * TV/Monitors
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
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April, 2006 - Rev. 8
Publication Order Number: NCP1603/D
NCP1603
+ AC Input EMI Filter Output Voltage - OVP NCP1603
Not Synchronized and VCC OVP Latch Implemented
+ AC Input EMI Filter Output Voltage -
NCP1603
OVP
Synchronized and Output OVP Latch Implemented Figure 1. Typical Application Circuits
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NCP1603
VFB2 FB2 2 5V 10V 20k 55k 0.75V 25k Gnd2 4 2.5 ms Softstart 1V max 100 kHz 5ms Jittering 0~2.3V ramp 18k CS2 3 VCS2 10V 3V 200ns LEB
+ - - +
start_Vaux 125 ms delay & &
Fault-1 Fault-2 disable Vaux when VCC2 < 7.7V
1
Vaux
Standby - 0.75V/ 1.25V
+
S RQ
Thermal Shutdown (140/165C) start_Vaux S 125 ms delay Q &
OR 3.2mA
initially disable Vaux
14 VCC2 20V
VSS 1
R
0 Error
latchoff, reset when VCC2 < 4V - Internal bias + OR + RQ SQ - 100 kHz S R OVP Max duty Fault-1 5ms Jittering = 80% latchoff, reset Oscillator when VCC2 < 4V PWM Fault-2 Voltage Regulator
Vreg
VCC2 mgmt (12.6 / 7.7V) (5.6 / 4V) VCC2
16 HV
13 Out2
PWM PFC
10 Vcontrol
VCC1
8 18V
UVLO (9 / 10.5V) Shutdown / UVP (IFB1 < 8% IREF) IFB1 9V IS 9V Current Mirror 45mA Current Mirror
300k
+ -
&
9V
Internal bias Overvoltage Protection (IFB1 > 107% IREF) Overcurrent Protection (IS > 203 mA) Zero Current Detection (IS < 14 mA) OR
+ -
96%I ref
I ref I FB1
C1 R1 0 1 R3 Ich 12
- +
Regulation Block
FB1
9
R2
C3
& 3.9V max clamp
CS1 11
Ramp
Vton PFC Modulation
9V
Osc
5 94mA
9V
Thermal Shutdown (95/140C) & delay
1
0
VCC1 7 Out1
clock SQ R R SQ
0
1
5/ 3.5 V
6
GND1
Figure 2. Functional Block Diagram
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PIN FUNCTION DESCRIPTION
Pin 1 Symbol Vaux Function Auxiliary Supply Description This pin connects to the VCC1 pin externally. It delivers a bias voltage from the VCC2 to the PFC section. The Vaux is disabled when either one of the following conditions occurs: (1) Vaux is initially off; (2) Fault (VFB2 > 3.0 V for more than 125 ms); (3) Standby (VFB2 < 0.75 V and then VFB2 is smaller than 1.25 V for more than 125 ms); (4) Overvoltage protection latch activated from CS2 pin; (5) Thermal shutdown latch in the PWM section; (6) Insufficient supply voltage (VCC2 < 7.7 V). The transistor turns on (or Vaux is enabled) when VFB2 is within the normal mode regulation window (0.75 V < VFB2 < 3.0 V). An external optocoupler collector pulls the voltage of this pin VFB2 down to regulate the output voltage. The PWM regulation window between VFB2 = 0.75 V and VFB2 = 3.0 V. When VFB2 drops below 0.75 V, the controller enters standby operation. When no feedback signal is received from the optocoupler, VFB2 is internally pulled to be higher than 3.0 V. If this condition lasts for longer than 125 ms, the controller enters double-hiccup fault condition. This pin cumulates three different functions: current-mode PWM regulation, primary overcurrent protection and overvoltage protection (OVP). If the voltage of this pin is above 3.0 V for OVP, the circuit is latched off until VCC2 resets. The PWM Drive Output is disabled. An external noise decoupling pF-order capacitor is connected to the pin to prevent the latch protection activated due to noise. - In oscillator mode, this pin is connected to an external capacitor to set the oscillator frequency in DCM operation. In synchronization mode, this pin is connected to an external driving signal. However, if the PFC-stage inductor current is non-zero at the end of a switching period, the PFC-stage circuit will be forced to CRM and the Out1 is out of synchronization to the Osc pin signal. - This pin provides an output to an external MOSFET in the PFC section. This pin is the positive supply of the PFC section. the operating range is between 9.0 V and 18 V with UVLO start threshold 10.5 V. This pin receives a current IFB1 that represents the PFC circuit output voltage. The current is for the output regulation, PFC section overvoltage protection (OVP) and PFC section output undervoltage protection (UVP). When IFB1 goes above 107% Iref, OVP is activated and the Drive Output is disabled. When IFB1 goes below 14 mA, the PFC section enters a low-current consumption shutdown mode. The control voltage Vcontrol directly controls the input impedance and hence the power factor of the circuit. This pin is connected to an external capacitor to limit the control voltage bandwidth typically below 20 Hz to achieve Power Factor Correction purpose. This pin receives a current IS that is proportional to the inductor current. The current is for overcurrent protection (OCP), and zero current detection. When IS goes above 200 mA, OCP is activated and the Drive Output (Out1) is disabled. When IS goes below 14 mA, it is recognized to be a zero current for feedback regulation and DCM or CRM operation in the PFC oscillator section. This pin is connected to an external capacitor to set a ramp signal. The capacitor value directly affects the input impedance of the PFC circuit and its maximum input power. This pin provides an output to an external MOSFET in the PWM section. This pin is basically the positive supply of the PWM section. It is also the positive supply of the whole device because the PFC section is also supplied from this pin indirectly through Vaux pin (Pin 1). The operating range is between 7.7 V and 18 V. The circuit resets when VCC2 drops below 4.0 V. This pin is for high voltage clearance of the HV pin. This pin connects to the bulk DC voltage to deliver power to the controller in startup or fault condition. The internal startup circuit is disabled in normal and standby condition for power saving purpose. The UVLO stop and start thresholds of the startup circuit are VCC2 = 12.6 V and VCC2 = 5.6 V.
2
FB2
PWM Feedback
3
CS2
PWM Current Sense
4 5
GND2 Osc
PWM Ground PFC Oscillator
6 7 8 9
GND1 Out1 VCC1 FB1
PFC Ground PFC Drive Output PFC Supply Voltage PFC Feedback
10
Vcontrol
PFC Control Voltage
11
CS1
PFC Current Sense
12 13 14
Ramp Out2 VCC2
PFC Ramp PWM Drive Output PWM Supply Voltage
15 16
NC HV
No Connected High Voltage
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MAXIMUM RATINGS
Rating Vaux Pin (Pin 1) Maximum Voltage Range Maximum Continuous Current FB2 and CS2 Pin (Pins 2-3) Maximum Voltage Range Maximum Current Ramp, CS1, Vcontrol, FB1, and Osc Pins (Pins 5, 9-12) Maximum Voltage Range Maximum Current Out1 Pin (Pin 7) Maximum Voltage Range Maximum Current VCC1 and VCC2 Pins (Pins 8, 14) Maximum Voltage Range Maximum Current Out2 Pin (Pin 13) Maximum Voltage Range Maximum Current HV Pin (Pin 16) Maximum Voltage Range Maximum Current Power Dissipation and Thermal Characteristics Maximum Power Dissipation (TA = 25C) Thermal Resistance, Junction-to-Air Operating Junction Temperature Range Maximum Storage Temperature Range Symbol Vmax Imax Vmax Imax Vmax Imax Vmax Imax Vmax Imax Vmax Imax Vmax Imax PD RqJA TJ Tstg Value -0.3 to +18 35 -0.3 to +10 100 -0.3 to +9.0 100 -0.3 to +18 -500 to +750 -0.3 to +18 100 -0.3 to +17.5 1.0 -0.3 to +500 100 770 111 -40 to +125 -60 to +150 Unit V mA V mA V mA V mA V mA V A V mA mW C/W C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device contains ESD protection and exceeds the following tests: Pin 1-14: Human Body Model 2000 V per Mil-Std-883, Method 3015. Machine Model Method 200 V. Pin 16 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V. 2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1603
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values, TJ = -40C to +125C, VCC2 = 13 V, HV = 30 V, VCC1 = 15 V, Vcontrol = 100 nF, Ramp = 330 pF, Osc = 220 pF unless otherwise specified).
Characteristic (PWM Section) PWM OSCILLATOR Oscillation Frequency (TJ = 25_C) (Note 3) Oscillation Frequency (TJ = 0_C to +125_C) Oscillation Frequency (TJ = -40_C to +125_C) Oscillator Modulation Swing, in Percentage of fosc2 Oscillator Modulation Swing Period Maximum Duty Ratio (VCS2 = 0 V, VFB2 = 2.0 V) PWM GATE DRIVE Gate Drive Resistor Output High (VCC2 = 13 V, Out2 = 300 W to GND2) Output Low (Out2 = 1.0 V, VFB2 = 0 V) Gate Drive Rise Time from 10% to 90% (Out2 = 1.0 nF to GND2) Gate Drive Fall Time from 90% to 10% (Out2 = 1.0 nF to GND2) PWM CURRENT SENSE/OVERVOLTAGE PROTECTION Maximum Current Threshold (TJ = 25_C) Maximum Current Threshold (TJ = -40_C to +125_C) Soft-Start Duration Leading Edge Blacking Duration Propagation Delay from CS Detected to Turn Out2 Off Overvoltage Protection Threshold Internal Compensation Ramp (Peak-to-Peak) (Note 4) Internal Resistor to Ramp (Note 4) PWM STANDBY THRESHOLDS/FEEDBACK Standby Thresholds Feedback Voltage VFB2 to Start Standby Feedback Voltage VFB2 to Stop Standby Validation Time for Leaving Standby Validation Time for Recognize a Fault Feedback Pin Sinking Capability (VFB2 = 0.75 V) AUXILIARY SUPPLY Vaux MOSFET Resistance (VCC2 = 13 V, VFB = 2.0 V, Vaux = 20 mA Sinking) PWM THERMAL SHUTDOWN Thermal Shutdown Threshold (Note 4) Thermal Shutdown Hysteresis PWM STARTUP CURRENT SOURCE High-Voltage Current Source Startup (VCC2 = VCC2(on)-0.2 V, VFB2 = 2.0 V, HV = 30 V) Startup (VCC2 = 0 V, HV = 30 V) Leakage (VCC2 = 13 V, HV = 700 V) Minimum Startup Voltage (VCC2 = VCC2(on)-0.2 V, IHV = 0.5 mA) 3. Consult factory for other frequency options. 4. Guaranteed by design. 16 IHV1 IHV2 IHV3 16 Vstart(min) 1.8 1.8 10 - 3.2 4.4 30 20 4.2 5.6 80 23 mA mA mA V - - TSD2 TH2 150 - 165 25 - - C C 1 Raux 6.0 11.7 23 W 2 Vstby Vstby-out 2 2 2 tstby-aux tfault IFB2 0.6 1.0 - - 200 0.75 1.25 125 125 235 0.9 1.5 - - 270 V V ms ms mA 3 - 3 - 3 3 3 ILimit tSS tLEB Tdelay(CS) VOVP Vcomp Rcomp 0.991 0.96 - 100 - 2.7 - 9.0 1.043 - 2.5 200 90 3.0 2.3 18 1.095 1.106 - 350 180 3.3 - 36 V ms ns ns V V kW 13 ROH2 ROL2 13 13 tr2 tf2 6.0 3.0 - - 12.3 7.5 40 15 25 18 - - W W ns ns - fosc2 93 90 85 - - 75 100 - - "6.4 5.0 80 107 110 110 - - 85 kHz Pin Symbol Min Typ Max Unit
- - -
- - Dmax
% ms %
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NCP1603
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values, TJ = -40C to +125C, VCC2 = 13 V, HV = 30 V, VCC1 = 15 V, Vcontrol = 100 nF, Ramp = 330 pF, Osc = 220 pF unless otherwise specified).
Characteristic (PFC Section) PWM SUPPLY SECTION Supply Voltage Startup Threshold, VCC2 Increasing Minimum Operating Valley Voltage after Turn-On Undervoltage Lockout Threshold Voltage, VCC2 Decreasing Logic Reset Level Supply Current Operating (VCC2 = 13 V, Out2 = Open, VFB2 = 2.0 V) Operating (VCC2 = 13 V, Out2 = 1.0 nF to GND2, VFB2 = 2.0 V) Latch-Off Phase (VCC2 = 6.5 V, VFB2 = 2.0 V) PFC OSCILLATOR Oscillator Frequency (Osc = 220 pF to GND) Internal Capacitance of the Oscillator Pin Maximum Oscillator Switching Frequency Oscillator Discharge Current (Osc = 5.5 V) Oscillator Charge Current (Osc = 3.0 V) Comparator Lower Threshold (Osc = 220 pF to GND) (Note 5) Comparator Upper Threshold (Osc = 220 pF to GND) Synchronization Pulse Width for Detection Synchronization Propagation Delay PFC GATE DRIVE Gate Drive Resistor Output High and Draw 100 mA out of Out1 Pin (Isource = 100 mA) Output Low and Insert 100 mA into Out1 Pin (Isink = 100 mA) Gate Drive Rise Time from 1.5 V to 13.5 V (Out1 = 1.0 nF to GND) Gate Drive Fall Time from 13.5 V to 1.5 V (Out1 = 1.0 nF to GND) 7 ROH1 ROL1 7 7 tr1 tf1 5.0 2.0 - - 11.6 7.2 53 32 20 18 - - W W ns ns 5 5 5 5 5 5 5 5 5 fosc1 Cosc(int) fosc1(max) Iodch Ioch Vsync(L) Vsync(H) tsync(min) tsync(d) 52 - - 40 40 3.0 4.5 500 - 58 36 405 49 45 3.5 5.0 - 371 64 - - 60 60 4.0 5.5 - - kHz pF kHz mA mA V V ns ns 14 VCC2(on) VCC2(off) VCC2(latch) VCC2(reset) 14 ICC2(op1) ICC2(op2) ICC2(latch) 0.6 1.3 400 1.1 2.2 680 1.8 3.0 1000 mA mA mA 11.6 7.0 5.0 - 12.6 7.7 5.6 4.0 13.6 8.4 6.2 - V V V V Pin Symbol Min Typ Max Unit
PFC FEEDBACK/OVERVOLTAGE PROTECTION/UNDERVOLTAGE PROTECTION Reference Current Regulation Block Ratio Vcontrol Pin Internal Resistor Maximum Control Voltage (IFB1 = 100 mA) Feedback Pin Voltage (IFB1 = 100 mA) Overvoltage Protection Current Ratio Overvoltage Protection Current Threshold Undervoltage Protection Current Threshold 5. Comparator lower threshold is also the synchronization threshold. 9 9 10 10 9 9 9 9 Iref IregL/Iref Rcontrol Vcontrol(max) VFB1-100 IOVP/Iref IOVP IUVP/Iref 192 95 - 0.95 - 104 - 4.0 203 96 300 1.05 3.0 107 217 8.0 208 97 - 1.15 - - 225 15 mA % kW V V % mA %
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ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25C, for min/max values, TJ = -40C to +125C, VCC2 = 13 V, HV = 30 V, VCC1 = 15 V, Vcontrol = 100 nF, Ramp = 330 pF, Osc = 220 pF unless otherwise specified).
Characteristic (PFC Section) PFC CURRENT SENSE Current Sense Pin Offset Voltage (IS = 100 mA) Overcurrent Protection Level Current Sense Pin Offset Voltage at Overcurrent Level Zero Current Detection Level Current Sense Pin Offset Voltage at Zero Current Level Zero Current Sense Resistor (RS(ZCD) = VS(ZCD)/IS(ZCD)) PFC RAMP Charging Current (Ramp = 0 V) Maximum Power Resistance (Rpower = Vcontrol(max)/Ich) Internal Clamping of Voltage Vton Internal Capacitance of the Ramp Pin Ramp Pin Sink Resistance (Osc = 0 V, Ramp = 1.0 mA sourcing) PFC THERMAL SHUTDOWN Thermal Shutdown Threshold (Note 6) Thermal Shutdown Hysteresis PFC SUPPLY SECTION Supply Voltage Startup Threshold (UVLO) Minimum Voltage for Operation after Turn-On UVLO Hysteresis Supply Current Start-Up (VCC1 = VCC1(on)-0.2 V) Operating (VCC1 = 15 V, Out1 = Open, Osc = 220 pF) Operating (VCC1 = 15 V, Out1 = 1.0 nF to GND1, Osc = 220 pF) Shutdown (VCC1 = 15 V, IFB = 0 A) 6. Guaranteed by design. 8 VCC1(on) VCC1(off) VH1 8 ICC1(stup) ICC1(op1) ICC1(op2) ICC1(stdn) - - - - 17 2.7 3.7 24 40 5.0 5.0 50 9.6 8.25 1.0 10.5 9.0 1.5 11.4 9.75 - V V V mA mA mA mA - - TSD1 TH1 140 - 170 45 - - C C 12 12 - 12 12 Ich Rpower Vton(max) Cramp(int) Rramp 95 9.5 - - - 100 10 3.9 22 71.5 105 11.5 - - - mA kW V pF W 11 11 11 11 11 11 VS IS(OCP) VS(OCP) IS(ZCD) VS(ZCD) RS(ZCD) - 190 0 9 0 - 4.0 203 3.2 14 7.5 0.536 - 210 20 19 20 1.0 mV mA mV mA mV kW Pin Symbol Min Typ Max Unit
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PWM SECTION OSCILLATOR FREQUENCY (kHz) PWM SECTION FREQUENCY JITTERING (%)
110 108 106 104 102 100 98 96 94 92 90 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
12 10 8 6 4 2 0 -50
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 3. PWM Section Oscillator Frequency vs. Temperature
PWM SECTION GATE DRIVE RESISTANCE (W)
Figure 4. PWM Section Oscillator Frequency Jittering vs. Temperature
PWM SECTION MAXIMUM DUTY (%)
85 84 83 82 81 80 79 78 77 76 75 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 CS2 Pin = 0 V FB2 Pin = 2 V
18 16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 ROL2 ROH2
Figure 5. PWM Section Maximum Duty vs. Temperature
Figure 6. PWM Section Gate Drive Resistance vs. Temperature
PWM SECTION SOFT-START PERIOD (ms)
1.1 PWM SECTION CURRENT LIMIT (V)
3 2.5 2 1.5 1 0.5 0 -50
1.05
1
0.95
0.9 -50
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 7. PWM Section Current Limit vs. Temperature
Figure 8. PWM Section Soft-Start Period vs. Temperature
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NCP1603
350 300 250 200 150 100 50 0 -50 PWM SECTION CS PROPAGATION DELAY (ns) PWM SECTION LEAD EDGE BLANKING (ns) 120 100 80 60 40 20 0 -50
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 9. PWM Section Lead Edge Blanking vs. Temperature
PWM SECTION CS PIN OVP THRESHOLD (V)
Figure 10. CS2 Pin Propagation Delay vs. Temperature
PWM SECTION MINIMUM PULSE (ns)
500 450 400 350 300 250 200 150 100 50 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 VCS2 = 2 V VFB2 = 2 V
3.15
3.1
3.05
3
2.95
2.9 -50
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 11. PWM Section Minimum Output Pulse vs. Temperature
PWM SECTION STANDBY THRESHOLDS (V)
Figure 12. CS2 Pin Overvoltage Protection Threshold vs. Temperature
1.4 PWM SECTION VALIDATION TIME FOR LEAVING STANDBY (ms) 125 1.2 1 0.8 0.6 0.4 0.2 0 -50 Vstby Vstby-out
160 140 120 100 80 60 40 20 0 -50
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 13. PWM Section Standby Thresholds vs. Temperature
Figure 14. PWM Section Validation Time for Leaving Standby vs. Temperature
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PWM SECTION FB PIN SINKING CAPABILITY (mA)
245 240 235 230 225 220 215 210 205 200 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 VFB2 = 0.75 V
PWM SECTION VALIDATION TIME FOR RECOGNIZE A FAULT (ms)
250
160 140 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 15. FB2 Pin Sinking Capability vs. Temperature
20 Vaux PIN MOSFET RESISTANCE (W) 18 16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 Vaux = 20 mA Sinking VCC2 = 13 V 6 5 4 3 2 1
Figure 16. PWM Section Validation Time for Recognizing a Fault vs. Temperature
STARTUP HIGH VOLTAGE CURRENT SOURCE (mA)
IHV1 (VCC2 = 0 V)
IHV2 (VCC2 = VCC2(on) - 0.2 V)
HV Pin = 30 V 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 17. Vaux Pin Internal MOSFET Resistance vs. Temperature
Figure 18. PWM Section High Voltage Startup Current Source vs. Temperature
HV PIN MINIMUM STARTUP VOLTAGE (V)
60 HV PIN LEAKAGE CURRENT (mA) 50 40 30 20 10 0 -50 HV Pin = 700 V VCC2 = 13 V
25 24 23 22 21 20 19 18 17 16 15 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 VCC2 = VCC2(on) - 0.2 V IHV = 0.5 mA
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 19. PWM Section HV Pin Leakage Current vs. Temperature
Figure 20. PWM Section HV Pin Minimum Operating Voltage vs. Temperature
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14 PWM SECTION SUPPLY VOLTAGE THRESHOLDS (V) 12 10 VCC2(off) 8 6 4 2 0 -50 VCC2(reset) VCC2(latch) VCC2(on) PWM SECTION SUPPLY CURRENTS (mA) 2.5
2
ICC2(op1) (VCC2 = 13 V, 1 nF Load) ICC2(op2) (VCC2 = 13 V, Out2 = Open)
1.5
1
0.5
ICC2(latch) (VCC2 = 6.5 V) VFB2 = 2 V
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
0 -50
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 21. PWM Section Supply Voltage Thresholds vs. Temperature
PFC SECTION OSCILLATOR FREQUENCY (kHz)
Figure 22. PWM Section Supply Currents vs. Temperature
60 59 58 57 56 55 54 53 52 51 50 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 PFC SECTION OSC PIN CHARGE AND DISCHARGE CURRENT (mA)
51 50 49 48 47 46 45 44 -50 Ioch (Osc Pin = 3 V) Iodch (Osc Pin = 5.5 V)
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 23. PFC Section Oscillator Frequency vs. Temperature
PFC SECTION GATE DRIVE RESISTANCE (W)
Figure 24. PFC Section Osc Pin Charge and Discharge Current vs. Temperature
5.5 PFC SECTION SYNCHRONIZATION THRESHOLDS (V) Vsync(H) 5
18 16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 ROL1 ROH1
4.5 COSC = 220 pF 4 Vsync(L) 3.5
3 -50
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 25. PFC Section Synchronization Thresholds vs. Temperature http://onsemi.com
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Figure 26. PFC Section Gate Drive Resistance vs. Temperature
NCP1603
PFC SECTION REFERENCE CURRENT (mA) 210 208 206 204 202 200 198 196 194 192 190 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 1.2 1 TJ = 25C 0.8 0.6 0.4 TJ = 125C 0.2 0 150 TJ = -40C
PFC SECTION REGULATION BLOCK (V)
160
170 180 190 200 IFB, FEEDBACK CURRENT (mA)
210
220
Figure 27. PFC Section Reference Current vs. Temperature
PFC SECTION REGULATION BLOCK RATIO (%)
Figure 28. PFC Section Regulation Block Transfer Function
99 98 97 96 95 94 93 92 91 90 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
PFC SECTION MAXIMUM CONTROL VOLTAGE (V)
100
1.1
1.08
1.06
1.04
IFB = 100 mA
1.02
125
1 -50
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 29. PFC Section Regulation Block vs. Temperature
Figure 30. PFC Section Maximum Control Voltage vs. Temperature
6 FB1 PIN OFFSET VOLTAGE (V) 5 TJ = 25C 4 3 2 1 0 0 50 100 150 200 IFB, FEEDBACK CURRENT (mA) 250 TJ = -40C PFC SECTION OVERVOLTAGE PROTECTION RATIO (%)
110 109.5 109 108.5 108 107.5 107 106.5 106 105.5 105 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
TJ = 125C
Figure 31. Feedback Pin Voltage vs. Feedback Current http://onsemi.com
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Figure 32. PFC Section Overvoltage Protection Ratio vs. Temperature
NCP1603
220 PFC SECTION OVERVOLTAGE PROTECTION THRESHOLD (mA) 218 216 214 212 210 208 206 204 202 200 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 10 PFC SECTION OVERVOLTAGE PROTECTION RATIO (%) 125 9 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 33. PFC Section Overvoltage Protection Threshold vs. Temperature
Figure 34. PFC Section Overvoltage Protection Ratio vs. Temperature
120 PFC SECTION CS PIN OFFSET (mV) CS1 PIN OFFSET VOLTAGE (mV) 100 80 60 40 TJ = -40C 20 0 0 50 100 150 200 IS1, CS1 PIN CURRENT (mA) 250 TJ = 125C TJ = 25C
10 9 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 VS(OCP) VS(ZCD)
Figure 35. CS1 Pin Offset Voltage vs. Current
PFC SECTION ZERO CURRENT THRESHOLD (mA)
Figure 36. PFC Section CS Pin Offset vs. Temperature
210 PFC SECTION OVERCURRENT PROTECTION THRESHOLD (mA) 208 206 204 202 200 198 196 194 192 190 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
15 14.5 14 13.5 13 12.5 12 11.5 11 10.5 10 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
Figure 37. PFC Section Overcurrent Protection Threshold vs. Temperature
Figure 38. PFC Section Zero Current Threshold vs. Temperature
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PFC SECTION CHARGING CURRENT (mA) 700 PFC SECTION ZERO CURRENT SENSE RESISTOR (W) 600 500 400 300 200 100 0 -50 105 104 103 102 101 100 99 98 97 96 95 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
PWM SECTION MAXIMUM POWER RESISTANCE (kW)
Figure 39. PFC Section Zero Current Sense Resistance vs. Temperature
Figure 40. PFC Section Charging Current vs. Temperature
11.5 11 10.5 10 9.5 9 8.5 8 -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
PFC SECTION SUPPLY VOLTAGE UVLO THRESHOLDS (V)
12
11 10.5 VCC1(on) 10 9.5 9 VCC1(off) 8.5 8 -50
125
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 41. PFC Section Maximum Power Resistance vs. Temperature
Figure 42. PFC Section Supply Voltage Undervoltage Lockout Thresholds vs. Temperature
PFC SECTION SUPPLY STARTUP AND SHUTDOWN CURRENTS (mA)
35 PFC SECTION OPERATING SUPPLY CURRENTS (mA) 30 25 20 15 10 5 0 -50 ICC1(stup) ICC1(stdn)
4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 -50 VCC1 = 15 V, COSC = 220 pF -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C) 125 ICC1(op1), No Load ICC1(op2), 1 nF Load
-25
0 25 50 75 100 TJ, JUNCTION TEMPERATURE (C)
125
Figure 43. PFC Section Supply Current in Startup and Shutdown Conditions vs. Temperature
Figure 44. PFC Section Operating Supply Currents vs. Temperature
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OPERATING DESCRIPTION
Vin EMI Filter L D1 Q1 Vbulk Cbulk Cosc IL IFB1 RFF ZOVP RFB1 RS1 RCS1 IS Ccontrol Cramp NCP1603 RS2 RCS2 ID Q2 Cs D2 + Vac Cfilter D3 Cout Vout Zref -
Figure 45. Typical Application Circuit
Introduction The NCP1603 is a PWM/PFC combo controller for two-stages PFC low-power application. A typical application circuit is listed in Figure 45. The first-stage PFC boost circuit draws a near-unity power factor current from the input but it also steps up the rectified input voltage Vin to a high bulk voltage Vbulk in the bulk capacitor Cbulk. Then, the second-stage PWM flyback circuit converts the bulk voltage Vbulk to a usable low voltage and isolated output voltage Vout. The controllers of the two stages are combined to become a single PWM/PFC combo controller. The advantages of NCP1603 are the following: 1. Integrated maximum 500 V lossless high voltage startup circuit that saves area and power loss. 2. Low standby power consumption because of PFC shutdown and skipping cycle operation. 3. Proprietary PFC methodology limits the maximum switching frequency and frequency jittering feature of the second-stage make the easier front-ended EMI filter design. 4. Internal ramp compensation for stability improvement in the second stage converter. 5. Minimum number of external components. 6. Optional synchronization capability between the PFC and PWM sections for bulk capacitor ripple current reduction. 7. Safety protection features. NCP1603 is a co-package of two individual IC dies. (NCP1601 and NCP1230, 100 kHz) The PFC die links up pin 5 to pin 12 that are in the lower half of Figure 46. The PWM die links up the other pins that are in the upper half of Figure 46. For simplicity, the PFC pins are named with suffix one that stands for the first stage and the PWM pins are named with suffix two that stands for the second stage. This dual-dies architecture allows the PFC die to be completely powered off in the standby low-power condition. It makes the power supply an excellent low-power no load standby performance.
Vaux 1 FB2 2 CS2 3 GND2 4 Osc 5 GND1 6 Out1 7 VCC1 8 PFC Die PWM Die
16 HV 15 NC 14 VCC2 13 Out2 12 Ramp 11 CS1 10 Vcontrol 9 FB1
Figure 46. Internal Connection Biasing the Controller
The PWM section is the master section that always operates. The PFC section is the slave section that is powered off in standby condition for power saving. It is implemented by connecting Vaux pin (Pin 1) and VCC1 pin (Pin 8) together externally. The VCC1 pin generally requires a small decoupling external capacitor (0.1 mF) or nothing. The PWM section powers the PFC section. The VCC of the whole device refers to VCC2 (Pin 14) in the PWM section (i.e., VCC = VCC2).
Vbulk
16
VCC2
14
NCP1603
1 4 6 8
CVCC GND1 = GND2
VCC1 = Vaux
Figure 47. Bias Supply Schematic
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The recommended biasing schematic of the controller is in Figure 47 while a typical completed application schematic can be referred to Figure 45. These two dies have their own individual supply voltages at Pin 8 and Pin 14. The grounds of the two dies are physically connected through the package substrate but they are needed to be connected externally. The bias voltage to the NCP1603 comes from the bulk voltage Vbulk through the HV pin (Pin 16) during startup. After startup, a second-stage flyback transformer auxiliary winding delivers the supply voltage to VCC.
Lossless High Voltage Startup Circuit
Vbulk HV 16 3.2 mA Turn Off UVLO QS R Double Hiccup B2 Counter 12.6/ 5.6 V 7.7 V - + & 20 V 7.7 V Turn on Internal Bias 12.6 V 18 V VCC1 (PFC) 9.0 V 10.5 V 18 V VCC 14 0.75 V Standby Condition (VFB2 < 0.75 V) VCC2 (PWM) + -
example, the PWM die consumes ICC2(op2) (2.2 mA typical), a 47 mF VCC capacitor can maintain the VCC above 7.7 V for 105 ms. It is the available time to establish a VCC voltage from the flyback transformer auxiliary winding.
C DV 47 mF*(12.6 V-7.7 V) tstartup + VCC + + 105 ms ICC2(op2) 2.2 mA (eq. 1)
A large enough VCC capacitor can also help to maintain VCC2 always above VCC2(off) to prevent the IC accidentally powered off during the standby condition where the low-frequency ripple of VCC2 can be very high. The PFC section does not consume any current in the startup phase since Vaux is disabled initially (i.e., Vaux = VCC1 = 0 V). When VCC2 falls below VCC2(off) (7.7 V typical) for whatever reason, the PWM section sleeps and it consumes ICC2(latch) (680 mA typical) until VCC2 reaches VCC2(latch) (5.6 V typical). When VCC2 reaches VCC2(latch) (5.6 V typical), the startup current source activates and VCC2 rises again.
VFB2 3.0 V Fault Condition (VFB2 > 3.0 V) Non- usable Vaux Enabled Region Usable Vaux Enabled Region
Figure 48. VCC2 Management
The HV pin (Pin 16) is capable of the maximum 500 V so that this pin can be directly connected to the bulk voltage Vbulk and delivers startup supply voltage to the controller. Figure 48 illustrates the block diagram of the startup circuit. An UVLO comparator monitors the VCC at Pin 14. A startup current source is activated and deactivated whenever the voltage reaches VCC2(latch) (5.6 V typical) and VCC2(on) (12.6 V typical) thresholds respectively. Therefore, the VCC never drops below VCC2(latch) after powering up unless the circuit is unplugged (i.e., Vbulk disappears or smaller than its minimum required operating threshold Vstart(min) (20 V typical)). This feature makes the controller memorize the external latch off function implemented in Pin 3. This in-chip startup circuit can minimize the number of external components and Printed Circuit Board (PCB) area. It also minimizes the loss due to startup resistor because startup resistor always dissipates power but this startup circuit can be turned off when the VCC voltage is sufficient. Actually, there is a small leakage current IHV3 (30 mA typical at HV = 700 V) when the startup circuit is off. The VCC capacitor is recommended to be at least 47 mF to ensure that VCC is always above the minimum operating voltage VCC2(off) (7.7 V typical) in the startup phase. For
Figure 49. Vaux Enabled Regions Auxiliary Supply Vaux
The Vaux pin (Pin 1) connects to the VCC1 pin (Pin 8) externally. Internally, the Vaux pin is connected to VCC2 through an internal MOSFET. The MOSFET on-resistance is Raux (11.7 W typical). It delivers a supply voltage from the PWM section to the PFC section. The Vaux is disabled when one of the following conditions occurs. 1. Vaux is initially disabled because of no feedback signal (VFB2 > 3.0 V) initially. 2. Fault condition (VFB2 > 3.0 V for more than 125 ms). 3. Standby condition (VFB2 < Vstby (0.75 V typical) and then VFB2 < Vstby-out (1.25 V typical) for more than 125 ms). 4. Insufficient operating supply voltage (VCC2 < VCC2(off) (7.7 V typical)). 5. Overvoltage protection (OVP) latch activated from CS2 pin (Pin 3) (VCS2 > VOVP (3.0 V typical)). 6. Thermal shutdown latch in the PWM section activated when the junction temperature is over typical 150_C.
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NCP1603
The UVLO start thresholds of VCC1 is VCC1(on) (10.5 V typical) and the maximum allowable limit is 18 V. On the other hand, the Vaux is enabled when VCC2 is over VCC2(off) (7.7 V typical). Hence, there are two possible operating regions in Figure 49. In the non-usable region the Vaux is not high enough to turn on the PFC section. Therefore, the flyback transformer auxiliary winding must be between VCC1(on) (10.5 V typical) and 18 V.
Regulation in the PWM Section
The PWM section (or the second stage) of the NCP1603 is NCP1230 that is a current-mode fixed-frequency PWM flyback controller with internal compensation ramp. The simplified block diagram of the duty cycle regulation section is in Figure 50. A 100 kHz clock oscillator is modulated by adding a frequency jittering feature. This modulated 100 kHz clock signal turns the Out2 (pin 13) high in each switching cycle. The Out2 goes low when the current-loop feedback signal intersects with the output voltage-loop feedback signal. A duty cycle is therefore generated. The maximum duty ratio is limited to Dmax (80% typical).
Vdd Vout 20 k 2 VFB2 55 k Soft-Start Processing Circuit 25 k 200 ns LEB - + PWM 2.3 V 0V 100 kHz Jittering Ramp 18 k VCC2 Out2 13 VFB2 3 VFB2 3 Vbulk 1 V Max Flyback Drain Current ID
FB2
Opto Coupler
Soft-Start Period 2.5 ms R S Max Duty = 80% Q
CS2 3 RS2 RCS2
6.4% Frequency Jittering Modulation
100 kHz Oscillator
Figure 50. Block Diagram of Duty Cycle Regulation in the PWM Section
The current-loop feedback circuit consists of a typical 200 ns Leading Edge Blanking (LEB) that is to prevent a premature reset of the output due to noise, a pair of sense resistors RCS2 and RS2 that sense the flyback drain current ID, and a 0-to-2.3 V jittering ramp that adds a ramp compensation for a stability improvement to the current-mode control possibly in continuous mode operation. The VFB2 is approximately divided by 3 by an internal pair of resistors (55 kW and 25 kW). The soft-start processing circuit reduces the initial voltage-loop feedback signal (VFB2 / 3) for 2.5 ms. After this 2.5 ms, the soft-start disappears. As a result, the startup envelope of the peak drain current (or duty ratio) ramps up gradually for 2.5 ms. It is noted that the 2.5 ms is counted when the PWM die circuit is reset that is when VCC2 reaches VCC2(on) (12.6 V typical). This soft-start feature offers a reduced
transient voltage and current stress on the power circuit during the startup. Excessive output voltage causes more the optocoupler current. It pulls down the VFB2 through FB2 pin (Pin 2) and generates a lower duty ratio. The output voltage reduces. Insufficient output voltage reduces the optocoupler current. If the current is too small, the VFB2 is eventually pulled high than 3.0 V (3.8 V typical). The (VFB2 /3) signal is then clamped to an internal 1.0 V limit. If the ramp is ignored (i.e., RS2 = 0), the maximum possible drain current is derived as:
ID(max) + 1 V RCS2
(eq. 2)
It is noted that resistor RS2 will affect the percentage of the ramp getting compared for the modulation. Hence, a large value of the RS2 increase the ramp and will reduce the possible maximum duty ratio.
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NCP1603
Frequency Jittering
PWM Section Oscillator Frequency
Fault Condition
106.4 kHz 100 kHz 93.6 kHz 5 ms time
Figure 51. Frequency Jittering of PWM Oscillator
Frequency jittering is a method used to soften the EMI signature by spreading the energy in the vicinity of the main switching component. The PWM Section offers a typical 6.4% deviation on the nominal switching frequency (100 kHz typical). A sweep sawtooth modulates the 100 kHz clock up and down with a 5.0 ms period. Figure 51 illustrates the 6.4% variation of the jittering oscillator frequency versus time.
Vdd
Figure 52 illustrates the fault detection circuitry and its timing diagram. When fault (or output short circuit) happens, the output voltage collapses and the optocoupler is opened. VFB2 is internally pulled to be higher than 3.0 V (3.8 V typical). Then, the controller activates an error flag when (VFB2/3) is greater than the soft-start voltage VSS that is 1.0 V after the 2.5 ms from startup. When the circuit is powering up in the beginning, the output voltage is not yet established and FB2 pin (Pin 2) is opened. Therefore, there is a 125 ms timer to allow the circuit to establish an initial output voltage. Then, a fault (or short circuit) condition is recognized when an error flag (VFB2 q 3.0 V) can last for 125 ms. When a fault is detected, Out2 (Pin 13) goes low. The power supply stops delivering power to the output. On the other hand, the Vaux (= VCC1) also goes low. The Vaux will restore immediately when the error flag disappears. This fault detection method offers advantage of getting rid of the auxiliary winding information that cannot truely represent the output voltage when the flyback transformer is badly coupled.
VFB2/3 20 k FB2 2 VFB2 55 k VFB2 3 VSS Start Vaux Enable Vaux/PFC + - 125 ms Delay 125ms Fault Disable Vaux/PFC and Out2 Vaux time 1V VSS time
&
25 k
Soft-Start 1 V Max
1V
Soft-Start Period 2.5 ms
Vaux starts when VFB2 is within regulation window (VFB2 < 3 V). (i.e., normal operation)
Vaux stops when VFB2 is out of regulation window (VFB2 > 3 V) for more than 125 ms. (i.e., fault condition)
Figure 52. Block Diagram and Timing Diagram of Fault Detection
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Startup current source charging the VCC capacitor 12.6 V VCC2 7.7 V 5.6 V Startup circuit turns on when VCC2 is 5.6 V Peak drain current follows a 2.5 ms soft-start envelope Maximum drain current is limited to 1 / RCS2 Startup circuit turns off when VCC2 is 12.6 V Circuit sleeps when VCC2 is below 7.7 V
ID 0A
time Switching starts when VCC2 reaches 12.6 V Switching is missing in every two VCC hiccup cycles featuring a "double hiccup"
Figure 53. Timing Diagram of Fault Condition
Figure 53 illustrates the timing diagram of VCC2 and the second-stage drain current ID in fault condition. The VCC drops because output voltage collapses. When VCC drops below VCC(off) (7.7 V typical), the Drive Output signal disappears and the VCC continues to drop. When bias voltage VCC drops to VCC(latch) (5.6 V typical), the startup current source activates and charge up the VCC until VCC reaches VCC(on) (12.6 V typical). The internal 2.5 ms soft-start activates after VCC reaches VCC(on) (12.6 V typical). The peak drain current follows its 2.5 ms envelope. The power supply dissipates some power due to the switching signal of Out2 and waits for possible auto-recovery of operation when the fault is cleared. As shown in Figure 53, NCP1603 has a "double hiccup" feature that allows the drain current in every two VCC hiccup cycle in fault condition. The "double hiccup" feature offers fewer power dissipation during fault condition comparing to "single hiccup". If the fault is cleared (VFB2 < 3.0 VSS) and VCC remains above VCC2(off) (7.7 V typical), the circuit will resume its operation. Otherwise, the VCC will continue this 12.6-7.7-5.6-12.6 V hiccup mode until the fault or bulk voltage is cleared.
Standby Condition
FB2
2
V FB2
Leave standby enable Vaux / PFC Section - + 125 ms delay & Standby disable Vaux/ PFC Section
0.75 V / 1.25 V
VFB2
1.25 V 0.75 V time
Vaux
125 ms time
Vaux stops when VFB2 is below 0.75 V and cannot go above 1.25 V for 125 ms
Vaux restores when VFB2 goes above 1.25 V
The output voltage rises up excessively in standby condition and the VFB2 drops. A set point of 25% of the maximum of VFB2 (i.e., 3.0 V) is defined to be the standby threshold. Hence, the standby threshold is Vstby = 25% x 3.0 V = 0.75 V.
Figure 54. Block Diagram and Timing Diagram of Standby Detection
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Figure 54 illustrates the standby detection circuitry and its timing diagram. When standby condition happens (i.e., VFB2 < 0.75 V), the controller will wait for a typical 125 ms to ensure that the output power remains low for a while. Then, the Vaux is disabled to shut down the PFC section for power saving. The Vaux (or the PFC) restores when VFB2 goes above 1.25 V immediately because VFB2 can be possibly above the 0.75 V threshold during standby operation (referring to Figure 55) and the PFC section is needed after the circuit restores from standby condition.
VCC2 needs to be above 7.7 V to ensure proper operation of the controller and main output within regulation VCC2 7.7 V Out2 goes low (no drain current) when VFB2 < 0.75 V 1.25 V 0.75 V VFB2
PFC in Discontinuous/Critical Mode
ID
time
Figure 55. Timing Diagram in Standby Condition
FB2 2
VFB2
- Standby + + - 0.75 V Vcc2 OR RQ S Out2 13
The PFC section of the NCP1603 is NCP1601 that is designed for low-power PFC boost circuit in DCM or CRM and takes advantages on both operating modes. DCM limits the maximum switching frequency. It simplifies the front-ended EMI filter design. CRM limits the maximum currents of diode, MOSFET and inductor. It reduces the costs and improves the reliability of the circuit. This device substantially exhibits unity power factor while operating in DCM and CRM. It minimizes the number of external components. The PFC section primarily designed to operate in fixed-frequency DCM. In the most stressful conditions, CRM can be an alternative option that is without power factor degradation. On the other hand, the PFC section can be viewed as a CRM controller with a frequency clamp (maximum switching frequency limit) alternative option that is also without power factor degradation. In summary, the PFC section can cover both CRM and DCM without power factor degradation. Based on the selections of the boost inductor and the oscillator frequency, the circuit is capable of the following three applications. 1. CRM only by setting the oscillator frequency higher than the CRM frequency range. 2. CRM and DCM by setting the oscillator frequency somewhere within the CRM frequency range. 3. DCM only by setting the oscillator frequency lower than the CRM frequency range.
Vin time Vcontrol
CS2 3
PWM
clock
time
Vton
Figure 56. Block Diagram in Standby Operation in PWM Section
time
Figure 55 and 56 show the timing diagram and block diagram of the standby operation respectively. A skipping cycle behavior of the drain current is made by reset the latch whenever VFB2 is smaller than 0.75 V. When VFB2 is greater than 0.75 V, the duty ratio is modulated by the PWM block that is illustrated in Figure 50.
current
Inductor current, IL Input current, Iin
time DCM critical mode DCM
Figure 57. Timing Diagram of the PFC Stage
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DCM needs higher peak inductor current comparing to CRM in the same averaged input current. Hence, CRM is generally preferred at around the sinusoidal peak for lower the maximum current stress but DCM is also preferred at the non-peak region to avoid excessive switching frequencies. Because of the variable-frequency feature of the CRM and constant-frequency feature of DCM, switching frequency is the maximum in the DCM region and hence the minimum switching frequency will be found at the moment of the sinusoidal peak.
DCM PFC Circuit
case of DCM when t3 = 0. When the PFC boost converter MOSFET is on, the inductor current IL increases from zero to Ipk for a time duration t1 with inductance L and input voltage Vin. Equation 3 is formulated.
Ipk Vin + L t1
(eq. 3)
The input filter capacitor Cfilter and the front-ended EMI filter absorb the high-frequency component of inductor current. It makes the input current Iin a low-frequency signal.
Iin + Ipk (t1 ) t2) for DCM 2T
(eq. 4)
A DCM/CRM PFC boost converter is shown in Figure 58. Input voltage is a rectified 50 or 60 Hz sinusoidal signal. The MOSFET is switching at a high frequency (typically around 100 kHz) so that the inductor current IL basically consists of high-frequency and low-frequency components.
Iin Vin Cfilter IL L Vout Cbulk
Ipk Iin + for CRM 2
(eq. 5)
From Equations 3, 4, and 5, the input impedance Zin is formulated.
V 2TL Zin + in + for DCM Iin t1(t1 ) t2) V Zin + in + 2L for CRM t1 Iin
(eq. 6)
(eq. 7)
Power factor is corrected when the input impedance Zin in Equations 6 and 7 are constant or slowly varying.
Figure 58. DCM/CRM PFC Boost Converter
Ich Ramp 12 Cramp closed when output low
Filter capacitor Cfilter is an essential and very small value capacitor in order to eliminate the high-frequency content of the DCM inductor current IL. This filter capacitor cannot be too bulky because it can pollute the power factor by distorting of the rectified sinusoidal input voltage.
PFC Methodology
PWM Comparator + - Vton Turns off MOSFET
The PFC section uses a proprietary PFC methodology particularly designed for both DCM and CRM operation. The PFC methodology is described in this section.
Inductor Current
Vton ramp out1
Figure 60. PFC Modulation Circuit and Timing Diagram
Ipk
The MOSFET on time t1 of PFC modulation duty is generated by a feedback signal Vton and a ramp. The PFC modulation circuit and timing diagram are shown in Figure 60. A relationship in Equation 8 is obtained.
t1 + Cramp Vton Ich
(eq. 8)
t1
t2 T
t3
time
Figure 59. Inductor Current in DCM
As shown in Figure 59, the inductor current IL of each switching cycle starts from zero in DCM. CRM is a special
The charging current Ich is constant 100 mA current and the ramp capacitor Cramp is constant for a particular design. Hence, according to Equation 8, the MOSFET on time t1 is proportional to Vton. In order to protect the PFC modulation comparator, the maximum voltage of Vton is limited to internal clamp Vton(max) (3.9 V typical) and the ramp pin (Pin 12) is with
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a 9.0 V ESD zener diode. The 3.9 V maximum limit of this Vton indirectly limits the maximum on time. The Vcontrol processing circuit generates Vton from control voltage Vcontrol and time information of zero inductor current. The circuit in Figure 61 makes Equations 9 and 10 where the value of resistor R1 is much higher than the value of resistor R2 (R1 >> R2).
closed when zero current R1 R2 Vreg
96% Iref
Iref IFB1
300k
Regulation Block
10 Vcontrol
Vcontrol Processing Circuit
Ccontrol
Figure 62. Vcontrol Low-Pass Filtering
C1 Vcontrol 10 Ccontrol - + R3 Vton C3
If the bandwidth of Vcontrol is much less than the 50 or 60 Hz line frequency, the input impedance Zin is slowly varying or roughly constant. Then, the power factor correction is achieved in DCM and CRM.
Maximum Power in PFC Section
Figure 61. Vcontrol Processing Circuit Vton + T Vcontrol for DCM t1 ) t2
(eq. 9) (eq. 10)
Input and output power (Pin and Pout) are derived in Equations 13 and 14 when the circuit efficiency is obtained or assumed. The variable Vac stands for the RMS input voltage.
Vac2CrampVcontrol V2 Pin + ac + Zin 2LIch Pout + h Pin + hVac2CrampVcontrol 2LIch
(eq. 13)
Vton + Vcontrol for CRM
It is noted that Vton is always greater than or equal to Vcontrol (Vton q Vcontrol). In summary, the input impedance Zin in Equation 11 is obtained from Equations 3 through 10.
2LIch V Zin + in + Iin Cramp Vcontrol
(eq. 11)
(eq. 14)
Control voltage Vcontrol comes from the PFC boost circuit output voltage (i.e., bulk voltage Vbulk) that is a slowly varying signal. The bandwidth of Vcontrol can be additionally limited by inserting an external capacitor Ccontrol to the Vcontrol pin (Pin 10) in Figure 62. The internal 300 kW resistor and the capacitor Ccontrol create a low-pass filter that has a bandwidth fcontrol in Equation 12. It is generally recommended to limit the bandwidth below 20 Hz to achieve power factor correction. Typical value of Ccontrol is 0.1 mF.
1 Ccontrol u 2p300kW fcontrol
(eq. 12)
From Equations 13 and 14, control voltage Vcontrol controls the amount of output power, input power, or input impedance. The maximum value of the control voltage Vcontrol is 1.05 V (i.e., Vcontrol(max) = 1.05 V). A parameter called maximum power resistor Rpower (10.5 kW typical) is defined in Equation 18 and restricted to have a maximum 10% variation (i.e., 9.5 kW p Rpower p 11.5 kW) for defining the maximum power in an application.
Rpower + Vcontrol(max) 1.05 V + + 10.5 kW 100 mA Ich
(eq. 15)
It means that the maximum input and output power (Pin(max) and Pout(max)) are limited to 10% variation.
Pin(max) + Vac2CrampRpower 2L hVac2CrampRpower 2L
(eq. 16)
Pout(max) +
(eq. 17)
The maximum input current Iac(max) to deliver the maximum input power Pin(max) is also derived in (eq.14). The suffix ac stands for RMS value.
Iac(max) + Pin(max) VacCrampRpower + 2L Vac
(eq. 18)
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Feedback in PFC Section
The output voltage of the PFC circuit (i.e., bulk voltage Vbulk) is sensed as a feedback current IFB1 flowing into the FB1 pin (Pin 9) of NCP1603. The FB1 pin voltage VFB1 is typically smaller than 5.0 V referring to Figure 31. It is much lower than Vbulk that is typically 400 V. Therefore, VFB1 is generally neglected.
V * VFB1 V IFB1 + bulk [ bulk RFB1 RFB1
(eq. 19)
where RFB1 is the feedback resistor connected the FB1 pin (Pin 9) and the output voltage referring to Figure 45. Then, the feedback current IFB1 represents the bulk voltage Vbulk and will be used in the PFC section voltage regulation, undervoltage protection (UVP), and overvoltage protection (OVP).
Bulk Voltage Regulation in PFC Section
The feedback resistor RFB1 consists of two or three high precision resistors in order to set the nominal Vbulk precisely and for safety purpose. The regulation block output Vreg is connected to control voltage Vcontrol through an internal resistor Rcontrol (300 kW typical) for the low-pass filter in Figure 62. The Vcontrol and the time information of zero current are collected in the Vcontrol processing circuit to generate Vton that is then compared to a ramp signal to generate the MOSFET on time t1 for power factor correction.
Current Sense in PFC Section
The PFC section senses the inductor current IL by the current sense scheme in Figure 64. This scheme has the advantages of: (1) the inrush current limitation by the resistor. RCS1. and (2) the overcurrent protection and zero current detection implemented in the same pin.
IL
PFC-stage feedback current IFB1, that presents bulk voltage Vbulk or the PFC-stage output voltage, is regulated with a reference current (Iref = 203 mA typical) as shown in Figure 63. When IFB1 is lower than 96% of Iref, the Vreg that is the output of the regulation block is as high as Vcontrol(max) (1.05 V typical) that it gives the maximum value on Vton and the maximum MOSFET on time and Vbulk increases. When IFB1 is higher than Iref, the Vreg becomes 0 V that gives no MOSFET on time and Vbulk decreases. As a result, the bulk voltage Vbulk is regulated around the range between 96% and 100% of the nominal value of RFB1 x Iref.
Vreg 1V
RS1
IS
CS1 + NCP1603 Gnd1 VS -
RCS1
IL
Figure 64. Current Sense in PFC Section
96% Iref
Iref
IFB1
Figure 63. Regulation Block
Based on Equations 13 and 14 for a particular power level, the Vcontrol is inversely proportional to Vac2. Hence, in high Vac condition Vcontrol is lower. It means that IFB1 or output voltage is higher based on the regulation block characteristic in Figure 63. In other words, the Vcontrol in the low Vac condition is much higher than the high Vac condition. In order to not over-design the circuit in the application, the Vcontrol in the low Vac condition is usually very closed to Vcontrol(max). It makes the output voltage be almost 96% of the nominal value of RFB1 x Iref in high Vac condition.
Inductor current IL passes through RCS1 and creates a negative voltage. This voltage is measured by a current IS flowing out of the CS1 pin (Pin 11). CS1 pin has an offset voltage VS. This offset voltage is studied in the setting of zero inductor current IL(ZCD) and the maximum inductor current IL(OCP) (i.e., overcurrent protection threshold). A typical variation of offset voltage VS versus sense current IS is shown in Figure 35. Based on Figure 64, Equation 20 is derived.
VS * RS1 IS + -RCS1 IL Zero Current Detection (ZCD) in PFC Section
(eq. 20)
The device recognizes zero inductor current when CS1 pin (Pin 11) sense current IS is smaller than IS(ZCD) (14 mA typical). The offset voltage of the CS1 pin in this condition is VS(ZCD) (7.5 mV typical). The inductor current IL(ZCD) at the ZCD condition is derived in Equation 21.
IL(ZCD) + RS1IS(ZCD) * VS(ZCD) RCS1
(eq. 21)
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It is obvious that the IL(ZCD) is not always zero. In order to make it reasonably close to zero, the setting of RS1 and RCS1 are crucial.
VS RS1 > RS(ZCD) Best ZCD point VS IL = 0 IL = IL(ZCD) IL > IL(ZCD)
Operating ZCD point RS1 = RS(ZCD) VS(ZCD) Ideal ZCD point IS IS(ZCD)
VS(ZCD)
IS IS(ZCD) Operating ZCD point
Figure 66. CS Pin Characteristic with Different Inductor Current
Figure 65. CS Pin Characteristic when IL = 0
Based on the CS pin (Pin 4) characteristics in Figure 35, Figure 65 is studied here. When the inductor current is exactly zero (i.e., IL(ZCD) = 0), the ideal ZCD point in the Figure 65 is reached where RS1 is RS(ZCD) (536 W typical). Considering the tolerance, the actual sense resistor RS1 is needed to be higher than the ideal value of RS(ZCD) to ensure that zero current signal is generated when sense current is smaller than the ZCD threshold (i.e., IS < IS(ZCD)). That is,
VS(ZCD) RS u RS(ZCD) + IS(ZCD)
(eq. 22)
It is noted in Figure 66 and Equation 23 that when the (RCS1 IL) term is smaller the error or distance between the lines to the line IL = 0 is smaller. Therefore, the value of the current sense resistor RCS1 is also recommended to be as small as possible to minimize the error in the zero current detection.
Overcurrent Protection (OCP) in PFC Section
Overcurrent protection is reached when IS is larger than IS(OCP) (200 mA typical). The offset voltage of the CS pin is VS(OCP) (3.2 mV typical) in this condition. That is:
IL(OCP) + RS1IS(OCP) * VS(OCP) RCS1
(eq. 24)
The higher value of RS1 makes the bigger distance between the operating and ideal ZCD points in Figure 65. Hence, RS1 has to be as low value as possible. The best recommended value of RS1 is therefore the maximum of RS(ZCD) that is 1.0 kW. Now that the RS1 is set at a particular value that is greater than RS(ZCD). From Equation 20, the operating lines in Equation 23 with different inductor currents IL of Equation 20 are studied.
VS + RS1IS * RCS1IL
(eq. 23)
When overcurrent protection threshold is reached, the Drive Output of the device goes low.
Oscillator/Synchronization Block in PFC Section
Oscillator Clock 45 mA Osc 5 94 mA 0 + - 5 V/3.5 V 1
Zero Current Turn on MOSFET
SQ R
&
These operating lines are added in Figure 65 to formulate Figure 66. When the inductor current IL is smaller than IL(ZCD), the sense current IS is smaller than IS(ZCD) and hence the zero current signal is generated.
delay
Figure 67. Oscillator / Synchronization Block in PFC Section
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The PFC section is designed to operate in either DCM or CRM. In order to keep the operation in DCM and CRM only, the Drive Output cannot turn on as long as there is some inductor current flowing through the circuit. Hence, the zero current signal is provided to the oscillator/ synchronization block in Figure 67. An input comparator monitors the Osc pin (Pin 5) voltage and generates a clock signal. The negative edge of the clock signal is stored in a RS latch. When zero current is detected, the RS latch will be reset and a set signal is sent to the output drive latch that turns on the MOSFET in the PFC boost circuit. Figure 68 illustrates a typical timing diagram of the oscillator block.
clock clock edge (latch set signal) clock latch (latch output) inductor current time Discontinuous mode Critical mode
700
C osc , Oscillator Capacitor (pF)
600 500 400 300 200 100 0 0 50 100 150 f osc , Oscillator Frequency (kHz) 200
Figure 70. Osc Pin Frequency Setting
Synchronization Option
Figure 68. Oscillator Block Timing Diagram
Oscillator Mode in PFC Section
In oscillator mode, the Osc pin (Pin 5) is connected to an external capacitor Cosc. When the voltage of this pin is above Vsync(H) (5.0 V typical), the pin sinks a current Iodch (94-45 = 49 mA typical) and the external capacitor Cosc discharges. When the voltage reaches Vsync(L) (3.5 V typical), the pin sources a current Ioch (45 mA typical) and the external capacitor Cosc is charged. It is noted that there is a typical 300 ns propagation delay and the 3.5 V and 5.0 V threshold conditions are measured on 220 pF Cosc capacitor. Hence, the actual oscillator hysteresis is a little bit smaller.
Osc pin voltage Osc clock Clock edge Drive output (DCM) 5V 3.5 V
In synchronization mode, the Osc pin (Pin 5) receives an external digital signal with level high defined to be higher than Vsync(H) (5.0 V typical) and level low defined to be lower than Vsync(L) (3.5 V typical). An internal 9.0 V ESD Zener diode is connected to the Osc pin and hence the maximum allowable synchronization voltage is 9.0 V. The circuit recognizes a synchronization frequency by the time difference between two falling edge instants when the synchronization signal across the 3.5 V threshold point. The actual synchronization threshold point is a little bit higher than the 3.5 V threshold point. The minimum synchronization pulse width is 500 ns. There is a typical 350 ns propagation delay from synchronization threshold point to the moment of output goes high and there is also a typical 300 ns propagation delay from the synchronization threshold point to the moment of crossing 3.5 V. Hence, the output goes high apparently when the sync signal turns to 3.5 V. A timing diagram of synchronization mode is summarized in Figure 71.
Sync Signal Osc Clock Clock Edge Drive Output (DCM) 5V 3.5 V
Figure 71. Synchronization Mode Timing Diagram in DCM
Figure 69. Oscillator Mode Timing Diagram in DCM
There is an internal capacitance Cosc(int) (36 pF typical) in the oscillator pin and the oscillator frequency is to fosc(max) (405 kHz typical) when the Osc pin is opened. Hence, the oscillator switching frequency can be formulated in Equation 25 and represented in Figure 70.
Cosc + 36 pF @ 405 kHz * 36 pF fosc
(eq. 25)
The PWM and PFC Section can be synchronized together in order to minimize some of the ripple current in the bulk capacitor as shown in Figure 72 and 73. The Out2 pin (Pin 13) is the external synchronization signal in Figure 71 to the PFC Section. When the Out2 is in high state, the voltage is potentially higher than the maximum allowable voltage in Osc pin (Pin 5). Hence, a pair of resistors divides the voltage from Out2 reduces the voltage
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entering Osc pin and a capacitor is added to remove some possible noise As a result, the current in Figure 73 may not necessarily passes through the bulk capacitor for fewer ripple current there.
NCP1603
Safety Features of NCP1603 (1) Bulk Voltage Overvoltage Protection (OVP)
Out2
OSC
When the PFC feedback current IFB1 is higher than 107% of the reference current Iref (i.e., the bulk voltage Vbulk is higher than 107% of its nominal value), the PFC Drive Output pin (Pin 7) of the device goes low for protection and the switch of the Vcontrol processing circuit is kept off. The circuit automatically resumes operation when the output voltage is lower than 107%. The maximum OVP threshold is limited to 225 mA that corresponds to 225 mA x 1.95 MW + 5.0 V = 443.75 V when RFB1 = 1.95 MW (e.g., 910 kW + 910 kW + 130 kW) and VFB1 = 5.0 V (for the worst case referring to Figure 31). Hence, it is generally recommended to use 450 V rating output capacitor to allow some design margin.
(2) Bulk Voltage Undervoltage Protection (UVP)
Figure 72. Synchronization Configuration
PWM drive PFC drive (DCM)
current
When the PFC feedback current IFB1 is smaller than 8% of the reference current Iref, the PFC section is shutdown and consumes less than 50 mA. In normal situation of the boost converter configuration, the output bulk voltage Vbulk is always higher than input voltage Vin and the IFB1 is higher than 8% of the reference current. It enables the PFC section to operate. Hence, UVP happens when the bulk voltage Vbulk is abnormally under-voltage, the FB1 pin (Pin 9) is opened, or the FB1 pin (Pin 9) is manually pulled low.
(3) PFC-Stage Overcurrent Protection
Phase 1
When the PFC sense current IS1 is higher than typically 200 mA, the PFC Drive Output (Pin 7) goes low. It represents the PFC-stage inductor current iL exceeds a user-defined value. The operation automatically resumes when the inductor current becomes lower than this user-defined value at the next clock cycle.
(4) PWM-Stage Short-Circuit Protection
current
Phase 2
Figure 73. Synchronization Timing Diagram
When VFB2 remains higher than 3.0 V for 125 ms, a fault is recognized. The PFC-stage (i.e., Vaux) will be disabled and the VCC2 will operate a double hiccup shown in Figure 53. The operation will be self-recovered if VCC2 is above 7.7 V and VFB2 is below 3.0 V. This fault protection is implemented by a timer and independent of badly coupled auxiliary transformer winding.
(5) Latched VCC Overvoltage Protection
Output Drive
The output stages of the PFC section and PWM section are designed for direct drive of power MOSFET. However, it is recommended to connect a current limiting resistor to the gate of the power MOSFET. The PFC section output is capable of up to -500 mA and +750 mA peak drive current and has a typical rise and fall time of 53 and 32 ns with a 1.0 nF load while the PWM section output is capable of up to "1.0 A peak drive current and has a typical rise and fall time of 40 ns and a fall time of 15 ns with a 1.0 nF capacitive load.
The normal operating voltage range of the CS2 pin (Pin 3) is between 0 V and Ilimit (1.0 V typical). When the voltage is above 1.0 V, the Out2 (Pin 13) goes low. When the voltage increases above 3.0 V, the Out2 goes low and stays latched off until the circuit is reset by unplugging from main supply to make VCC2 drop below VCC(reset) (4.0 V typical). This feature also offers the designer the flexibility to implement an externally pull-high latched protection or latched shutdown circuit.
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In order to prevent wrongly triggering the latch protection function, it is generaly recommended to put a pF-order decoupling ceramic capacitor across the CS2 pin to remove possible high-frequency noise there. To set the VCC overvoltage protection, the circuit is configured in Figure 74. A PNP bipolar transistor is added to open the Zener diode ZOVP when Out2 is high in order to stop any interference of the normal operation of current sense. It is because the Zener diode easily pulls high the CS2 pin voltage to 1.0 V and that interferes with the normal operation of the current sense when the output is high. The OVP threshold VCC2(OVP) is expressed in Equation 26.
VCC2(OVP) + VZOVP ) 3 V
VCC2 (eq. 26)
leakage current of the zener diode due to temperature variation. The Zener diode at the output voltage is recommended to be a 1 mA operating current at the threshold voltage. Then, this current is coupled through the optocoupler and inserts a similar order of current (depending on the current-transfer-ratio CTR of the optocoupler) into CS2 pin. The CS2 pin is capable of up to 100 mA and with an internal 9 V anti-parallel ESD diode but it is recommended to put a 8.2 V Zener diode there to further protect the pin.
VCC2 Vout
CS2
NCP1603
ZOVP
CS2
NCP1603
ZOVP RS2 RCS2 RS2
Figure 75. Output Latched OVP Application Circuit
RCS2
(7) Dual Thermal Shutdown (TSD) Figure 74. VCC Latched OVP Application Circuit (6) Latched Overvoltage Protection (OVP)
As long as an external protection on CS2 pin (Pin 3) does not affect the normal regulation operation of current sense, the protection can be implemented. An alternative is to implement the output overvoltage protection by an optocoupler in Figure 75. The leakage current of the added circuit is up to the zener diode at the output voltage. When there is no overvoltage, the leakage is small and it does not affect the normal operation. A resistor paralleled to the optocoupler is added to share the potential increasing
The NCP1603 consists of two individual dies that incorporates their individual thermal shutdown. The PFC thermal circuitry disables the PFC gate drive Out1 and then keeps the power switch off when its junction temperature exceeds 170 C typically. The PFC gate drive Out1 is then enabled once the temperature drops below typically 125C (i.e., 45C hysteresis). The PWM thermal circuitry disables the PWM gate drive Out2 and then keeps the power switch off when its junction temperature exceeds 165C typically. The PWM gate drive Out2 is then enabled once the temperature drops below typically 140C and the circuit is unplugged (to make VCC2 drops below 4.0 V).
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PFC Toggling
The variation of the duty ratio in the PWM stage between the PFC-on or PFC-off can be very large. When the NCP1603 circuit is operating at some conditions between PFC on and off boundary, the duty ratio variation can lead to unwanted on/off toggling in the PFC stage. A current feedforward resistor RFF is hence recommended to added between Vaux and CS2 pin (pins 1 and 3) in Figure 76 to prevent the toggling. The value of RFF is much larger than current sense feedback resistor RS2 and plays very little effect when Vaux = 0 (or PFC is off). When Vaux is available (or PFC is on), the RFF creates a positive offset on the CS2 pin voltage and it allows the feedback voltage VFB2 to only shift slightly but provide a dramatic duty cycle reduction in Figure 77. It slight movement of the feedback voltage can reduce the change to reach the PFC stage on/off threshold. Hence, the current feedforward resistor can help to improve the toggling.
Vbulk
Vaux
VFB2 3 VCS2
Out 2
High duty when PFC is off.
Low duty when PFC is on.
Figure 77. Timing Diagram of PWM Stage When RFF is Added
RFF
Vaux
CS2
NCP1603
RS2
Figure 76. Feedforward Resistor RFF Added
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PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9
-B- P
1 8
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
The products described herein (NCP1603), may be covered by one or more of the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,221, 6,970,365. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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